Integrated circuit fabrication techniques vary greatly depending on the specific chip structure being made, the exact processes being used, and/or the available equipment. However, almost all fabrication methods include a lithography process during which certain regions of a wafer (i.e., a silicon slice coated with a photoresist material) are exposed to radiation to delineate a latent image corresponding to the desired circuit pattern. The radiation-exposed wafer is then developed, etched, and processed to form an integrated circuit.
The technical advances in lithography processes have been significant. Integrated circuits built to design rules at or slightly below 0.25 .mu.m are common with the use of radiation in the deep ultraviolet wavelength. Radiation in the extreme ultraviolet (EUV) range (3 nm to 50 nm wavelength--also referred to as "soft x-ray") has been found useful for the fabrication of devices having design rules of 0.18 .mu.m and is prospectively useful for even smaller design rules, such as 0.10 .mu.m and smaller.
During the past eight years, EUV lithography has evolved from a simple concept into a possible candidate for mass commercial production of integrated circuits. Projection lithography, and particularly reflective (rather than transmission) projection lithography, is believed to be the best route to industrial production of integrated circuits by use of EUV lithography. In such a system, EUV radiation is projected onto a lithography mask having reflective regions and non-reflective regions corresponding to the desired circuit pattern. The beams reflected from the mask are then demagnified and projected onto the wafer.
Of particular interest in the present invention is the reflective mask used in EUV projection lithography. A reflective EUV mask may be viewed as comprising a pattern-producing portion and a substrate supporting the pattern-producing portion on top thereof. The pattern-producing portion comprises a reflective coating on the substrate layer and a plurality of absorbing blocks covering selective regions of the reflective coating. The absorbing blocks and the covered regions of the reflective coating form non-reflective regions of the mask. The uncovered portions of the reflective coating form the reflective regions of the mask.
Since the reflective coating is applied to a top surface of the substrate, it is important that this surface be as flat as possible. Otherwise, the substrate's non-smoothness will be translated (and perhaps exaggerated) in the coating thereby affecting its reflecting accuracy. Another issue which must be taken into consideration with a reflective EUV mask is expansion due to thermal conditions. Specifically, because the absorbing blocks (or non-reflective regions) of the mask absorb rather than reflect the radiation, they absorb heat and this heat is conducted through the reflective coating to the substrate. If the substrate expands upon conduction of this heat, this expansion could cause variations in the mask's dimensions that result in registration errors.
As far as flatness is concerned, silicon is usually the substrate material of choice. The top surface of a silicon slice may be polished to have excellent surface flatness specifications. However, silicon, has a relatively high coefficient of thermal expansion (CTE), specifically 2.5 ppm/.degree. C. Thus, despite its "flatness" attributes, a silicon substrate may present thermal expansion issues.
Accordingly, the inventor appreciated that a need remains for a reflective lithography mask which accommodates both optical flatness concerns and thermal expansion concerns without having to make a significant compromise therebetween.